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| ispPAC 80 TM In-System Programmable Analog Circuit Features * IN-SYSTEM PROGRAMMABLE (ISPTM) ANALOG -- Instrument Amplifier Gain Stage -- Precision Active Filtering (50kHz to 500kHz) -- Continuous-Time Fifth Order Low Pass Topology -- Dual, A/B Configuration Memory -- Non-Volatile E2CMOS Cells -- IEEE 1149.1 JTAG Serial Port Programming * UNIQUE FLEXIBILITY AND PERFORMANCE -- Programmable Gain Range (0dB to 20dB) -- Implements Multiple Filter Types: Elliptical, Chebyshev, Bessel, Butterworth, Linear Phase, Gaussian and Legendre -- Low Distortion (THD < -74dB max @ 100kHz) -- Auto-Calibrated Input Offset Voltage * TRUE DIFFERENTIAL I/O -- High CMR (58dB) Instrument Amplifier Input -- 2.5V Common Mode Reference on Chip -- Rail-to-Rail Voltage Outputs * SINGLE SUPPLY 5V OPERATION -- Power Dissipation of 165mW -- 16-Pin Plastic SOIC, PDIP Packages * APPLICATIONS INCLUDE INTEGRATED -- Single +5V Supply Signal Conditioning -- Programmable Filters With Fully Differential I/O -- Analog Front Ends, 12-Bit Data Acq. Systems -- DSP System Front End Signal Conditioning -- High-Performance Reconstruction Filters Functional Block Diagram TMS TCK TDI TDO CS CAL ENSPI GND 1 2 IA OA 16 VS 15 TEST 14 OUT+ 5th Order LPF E2CMOS Cfg A Ref & Auto-Cal E2CMOS Cfg B ISP Control 3 4 5 6 7 8 13 OUT- 12 TEST 11 IN+ 10 IN- 9 VREFOUT ispPAC80 Description The ispPAC80 is a member of the Lattice family of In-System Programmable analog circuits, digitally configured via nonvolatile E2CMOS(R) technology. Analog building blocks, called PACellTM(s), replace traditional analog components such as opamps, eliminating the need for external resistors and capacitors. With no requirement for external configuration components, ispPAC80 expedites the design process, simplifying prototype circuit implementation and change, while providing high-performance integrated functionality. With all components on chip, there is no longer a concern of performance degradation due to component mismatch or other external factors. The ispPAC80 provides reliable and repeatable performance, every time. Designers configure the ispPAC80 and verify its performance using PAC-DesignerTM, an easy to use, Microsoft Windows(R) compatible program. A filter configuration database is provided whereby thousands of different configurations can be realized. No special understanding of filter synthesis is required beyond that of general specifications such as corner frequency and stopband attenuation, etc. The software lists the possible choices that meet the designer's specifications which can then be loaded directly into either of two device (A/B) configurations from the lookup table. Device programming is supported using PC parallel port I/O operations. The ispPAC80 is configured through its IEEE Standard 1149.1 compliant serial port. The flexible In-System Programming capability enables programming, verification and reconfiguration, if desired, directly on the printed circuit board. Typical Application Diagram 5V ispPAC80 5V 12-Bit Differential Input ADC Ain+ AinA/B & Gain SPI Control VREFout Reference Vin 5V DSP Copyright (c) 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-888-477-7537; FAX (503) 268-8037; http://www.latticesemi.com March 2000 pac80_03 1 Specifications ispPAC80 TA = 25C; VS = 5.0V; 1V < VOUT < 4V; Gain = 1; Output load = 200pF, 1M. Filter configuration = CC051042, FP = 50kHz; Auto-Cal initiated immediately prior. (Unless otherwise specified). DC Electrical Characteristics Symbol Parameter Condition Applied to Either VIN+ or VIN2| VIN+ - VIN-| G = 10 G=1 -40 to +85C Min. 1 6 30 0.3 40 109 2 1 80 0.1 9.6 10 2.495 0 0.5 20 80 70 -0.2 50 50 350 40 80 10K 0 2 0VTCK,ENSPI,CAL Input VS 0VTDI,TMS,CSb Inputs VS IOL = 4.0mA IOH = -1.0mA 1M 0.8 VS -10/+40 -70/+10 0.5 Typ. Max. 4 200 2 Units V Vp-p V mV V/C pF pA nV/Hz V Vp-p mA V dB % ppm/C dB dB % ppm/C A A VRMS dB cycles V V A A V V Analog Input VIN (1) Input Voltage Range VIN-DIFF Differential Input Voltage Swing (2) VOS (2) Differential Offset Voltage (Input Referred) VOS/T Differential Offset Voltage Drift RIN Input Resistance CIN Input Capacitance IB Input Bias Current eN Input Noise Voltage Density Analog Output VOUT Output Voltage Range VOUT-DIFF Differential Output Voltage Swing (2) IOUT Output Current VCM Common Mode Output Voltage Static Performance G Programmable Gain Range Gain Error G/T Gain Drift PSR Power Supply Rejection Common Mode Reference Output (VREFOUT) VREFOUT Reference Output Voltage Range Reference Output Voltage Drift IREFOUT Reference Output Current Reference Output Noise Voltage Reference Power Supply Rejection Programming Erase/Reprogram Cycles Digital I/O VIL VIH IIL, IIH VOL VOH Input Low Voltage Input High Voltage Input Leakage Current Output Low Voltage (TDO) Output High Voltage (TDO) at DC At 10kHz, Referred to Input, G = 10 Present at Either VOUT+ or VOUT- 2| VOUT+ - VOUT- | Source/Sink (VOUT+ + VOUT-)/2 Input Gain Amplifier (1, 2, 5, 10) RL = 300 Differential -40 to +85C Differential at 1kHz Single-ended at 1kHz Nominally 2.500V -40 to +85C (VREFOUT = 1%) Source (VREFOUT = 1%) Sink 10MHz Bandwidth 1kHz 4.9 2.5 2.505 20 2.5 0.2 2.4 2 Specifications ispPAC80 AC Electrical Characteristics Symbol Parameter Dynamic Performance (4) SNR Signal to Noise (G=1 to 10) THD Total Harmonic Distortion (Differential) Single-Ended Differential (FP = 500kHz) Single-Ended (FP = 500kHz) CMR Common Mode Rejection (VIN = 1V to 4V) Note: VIN+ and VIN- connected together Filter Characteristics (4) FC Corner Frequency Programming Range |FC| Absolute Corner Frequency Accuracy FC FC/T Maximum Delta Between Corner Frequencies Corner Frequency Delta vs. Temperature Condition 0.1Hz to 500kHz, FC = 500kHz FIN = 10kHz, VIN = 6Vp-p FIN = 10kHz, VIN = 6Vp-p FIN = 100kHz, VIN = 6Vp-p FIN = 100kHz, VIN = 6Vp-p 10kHz 100kHz, FC = 500kHz Elliptic Filter Families Deviation From Calculated -3dB point FC = 50, 200 or 500kHZ 50kHz to 500kHz FC = 50kHz FC = 500kHz FC = 50kHz 50 0.6 Min. Typ. 83 -90 -80 -90 -74 60 60 Max. Units dB dB dB dB dB dB dB kHz % % %/C %/V dB dB 5.25 40 210 85 150 V mA mW C C -74 -74 50 500 3 3.7 FC/V Corner Frequency Delta vs. Supply Voltage Elliptic Filter Response (5) Passband Ripple FC = 50kHz FC = 500kHz Power Supplies VS Operating Supply Voltage IS Supply Current PD Power Dissipation Temperature Range Operation Storage 0.03 0.05 0.09 0.1 0.5 4.75 VS = 5.0V VS = 5.0V -40 -65 5 33 Notes: (1) A wider input range of 0.7V to 4.3V is typical, but not guaranteed. Inputs larger than this will be clipped. Input signals are also subject to common-mode voltage limitations. Refer to the table of conditions in this datasheet. (2) Refer to theory of operation section later in this datasheet for explanation of differential voltage swing computation. (3) To insure full spec performance an additional auto-calibration should be performed after initial turn-on and the device reaches thermal stability. (4) Although many hundreds of thousands of filter configurations are available using ispPAC80, not every type will have corner frequencies available from exactly 50kHz to 500kHz, depending on the tables available from within PACDesigner filter design tools. The general specifications given under this heading are realized using the Elliptic filter types. (5) A Cauer elliptic filter of type CC051042 (see datasheet text) is used to guarantee these specific filter accuracy specifications. It is assumed that all other configurations available in PAC-Designer will exhibit equivalent performance according to the applicability of the individual filter type. Necessary limitations will apply, however, when specifications do not directly apply. See the data sheet text, application notes and guides in PAC-Designer for specific filter type considerations. 3 Specifications ispPAC80 Absolute Maximum Ratings Supply Voltage VS ....................................... -0.5 to +7V Logic and Analog Input Voltage Applied ........... 0 to VS Logic and Analog Output Short Circuit Duration ..... Indefinite Lead Temperature (Soldering, 10 sec.) .............. 260C Ambient Temperature with Power Applied ... -55 to 125C Storage Temperature ................................ -65 to 150C Note: Stresses above those listed may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied. Package Options 1 16-pin PDIP Part Number Description ispPAC 80 - XX X X Device Family Device Number Performance Grade 01 = Standard Package P = PDIP, S = SOIC Grade I = Industrial Temperature ispPAC 80 1 16-pin SOIC ispPAC 80 ispPAC80 Ordering Information Ordering Number ispPAC80-01PI ISPPAC80-01SI Package 16-Pin PDIP 16-Pin SOIC 4 Specifications ispPAC80 Timing Specifications (JTAG Interface Mode) TA = 25C; VS = +5.0V (Unless otherwise specified) Symbol Dynamic Performance Parameter Condition Min. Typ. Max. Units tckmin tckh tckl tmss tmsh tdis tdih tdozx tdov tdoxz tpwp tpwe tpwcal1 tcalmin tpwcal2 Minimum Clock Period TCK High Time TCK Low Time TMS Setup Time TMS Hold Time TDI Setup Time TDI Hold Time TDO Float to Valid Delay TDO Valid Delay TDO Valid to Float Delay Time for a programming operation Executed in Run-Test/Idle Time for an erase operation Executed in Run-Test/Idle Time for auto-cal operation on power-up Automatically executed at power-up Minimum auto-cal pulse width Time for user initiated auto-cal operation Executed on rising edge of CAL tckh tckl tckmin TCK 200 50 50 15 10 15 10 60 60 60 100 100 250 100 80 80 40 ns ns ns ns ns ns ns ns ns ns ms ms ms ns ms tpwp, tpwe TCK tmss tmsh tmss *(PRGUSR/UBE executed in Run-Test/Idle state) tmss TMS tdis tdih TMS TDI tdozx tdov tdoxz CAL tcalmin (Note: CAL internally initiated at device turn-on.) VOUT = 0VDIFF TDO VOUT tpwcal1, tpwcal2 *Note: During device JTAG programming, analog output response will deviate from expected behavior. This is because all configuration information is erased and then re-written as part of a normal programming cycle, momentarily changing device filter and gain parameters. Behavior will deviate from that expected during both of these steps since the analog outputs are not clamped during a programming cycle. During erase, a drop in the filter corner frequency and an automatic change to the 10X gain setting can be expected (80ms minimum by specification) and will continue until bits go to there final state after a JTAG write command is issued (less than 2ms later, though the write cycle must still be maintained for a full 80ms to achieve specified data retention). 5 Specifications ispPAC80 Timing Specifications (SPI Interface Mode) TA = 25C; VS = +5.0V (Unless otherwise specified) Symbol Parameter Dynamic Performance tckmin Minimum Clock Period tckh TCK High Time tckl TCK Low Time tcss CS Setup Time tcsminhi Minimum CS Pulse Widths tdis TDI Setup Time tdih TDI Hold Time tdozx TDO Float to Valid Delay tdov TDO Valid Delay tdoxz TDO Valid to Float Delay Condition Min. 200 100 100 20 40 15 10 60 60 60 Typ. Max. Units ns ns ns ns ns ns ns ns ns ns tckmin TCK tckh tckl tcss CS tdis tdih tcsminhi TDI tdozx TDO tdov tdoxz hi-z hi-z 6 Specifications ispPAC80 Pin Descriptions Pin(s) 1 2 3 4 5 6 7 8 9 10, 11 12, 15 13, 14 16 Symbol TMS TCK TDI TDO CS CAL ENSPI GND VREFout IN TEST OUT VS Name Test Mode Select Test Clock Test Data In Test Data Out Chip Select Auto-Calibrate Enable SPI Mode Ground Common-Mode Reference Inputs (+ or -) Test Pin Outputs (+ or -) Supply Voltage Description Serial interface logic mode select pin (input). JTAG interface mode only. Serial interface logic clock pin (input). JTAG interface mode only. Serial interface logic pin (input) for both JTAG and SPI operation modes. Input data valid on rising edge of TCK (JTAG), or on rising edge of CS (SPI). Serial interface logic pin (output) for both JTAG and SPI operation modes. Input data valid on falling edge of TCK (JTAG), or on rising edge of CS (SPI). Chip select logic input pin. SPI data latch. Digital pin (input). Commands an auto-calibration sequence on a rising edge. Enable SPI logic input pin. When high, causes serial port to run in SPI mode. Ground pin. Should normally be connected to the analog ground plane. Common-mode voltage reference output pin (+2.5V nominal). Must be bypassed to GND with a 1F capacitor. Differential input pins, using two pins (e.g., IN+ and IN-). Plus or minus components of VIN, where differential VIN = VIN+ - VIN-. Test pin. Connect to GND for proper circuit operation. Differential output pins, using two pins (e.g., OUT+ and OUT-). Complementary with respect to VREFOUT. Differential VOUT = VOUT+ - VOUT-. Analog supply voltage pin (5V nominal). Should be bypassed to GND with 1F and .01F capacitors. Connection Notes 1. All inputs and outputs are labeled with plus (+) and minus (-) signs. Polarity is labeled for reference and can be selected externally by reversing pin connections. 2. All analog output pins are "hard-wired" to internal output devices and should be left open if not used. VOUT+ and VOUT- should not be tied together as unnecessary power will be dissipated. 3. When the signal input is single-ended, the other half of the unused differential input must be connected to a DC common-mode reference (usually VREFOUT, 2.5V). 7 Specifications ispPAC80 Typical Performance Characteristics Input Noise Spectrum 10K 90 CMR vs. Frequency 90 PSR vs. Frequency Common Mode Rejection (dB) Power Supply Rejection (dB) 1M 80 Noise Voltage (nVHz) Elliptical filter cc051042 Fc = 50kHz 80 1K G=1 70 70 60 60 100 G = 10 (Referred to Input) 50 40 Elliptical filter cc051042 Fc = 500kHz 50 40 30 10 1 10 100 1k 10k 100k 1M Frequency (Hz) 30 10 100 1k 10k 100k Frequency (Hz) 100 1k 10k 100k Frequency (Hz) 1M THD vs. Frequency -70 30 VOS Tempco 3 Wafer Lots PDIP Pkg -40C to +85C 0 dB Filter Variation (3 Sigma) Passband ripple variation over process < 0.02dB Total Harmonic Distortion (dB) -75 Percentage of Devices (%) Elliptical filter cc051042 Fc = 500kHz G=1 25 -80 20 -40 dB Stopband attenuation variation over process < 0.9dB -85 15 -90 -95 -100 G = 10 10 -80 dB Elliptical filter cc051042 5 0 1k 10k 100k Frequency (Hz) 1M -100 -50 0 50 100 Offset Tempco (V/C) 10kHz 100kHz 1MHz 50 kHz Corner Freq. Error 200 Units PDIP Pkg 30 Elliptical filter cc051042 200 kHz Corner Freq. Error 200 Units PDIP Pkg Elliptical filter cc051042 500 kHz Corner Freq. Error 200 Units PDIP Pkg Elliptical filter cc051042 30 Percentage of Devices (%) 25 20 15 10 5 Percentage of Devices (%) 50 Percentage of Devices (%) 25 40 20 15 30 20 10 5 10 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 Corner Frequency Error (%) Corner Frequency Error (%) Corner Frequency Error (%) 8 Specifications ispPAC80 Theory of Operation Reference Configuration In the specifications table, specific filter configurations are referred to, such as the CC051042. This is simply a shorthand notation for the classical filter type that includes all the characteristic parameters of the particular configuration. In this case, the CC refers to complete Chebyshev, or a Chebyshev ripple response in both the pass and stopbands of the filter. Another common name for this type of filter is the Elliptic family of filters. The next set of numbers, "05" refers to the order of the filter. In the case of ispPAC80 this will always be fifth order. The next two digits signify the reflection coefficient (rf), in this case 10%, and has a direct mathematical relationship to the passband ripple magnitude of the filter, where the passband ripple expressed in dB = 10*Log(1-rf2). The final two digits are the passband to stopband attenuation ratio expressed as an angle, in this case 42 degrees or 1.49 (1/sin((/180)*42)). This configuration corresponds to the elliptical filter with the ID# 3083 (Fp=50.00kHz; Figure 1. Simplified ispPAC80 Filter Core Schematic R21 100K R32 -100K Fc=56.23kHz) in the filter configuration database utility of PAC-Designer. Because of the almost limitless number of configurations realizable with ispPAC80, standard test configurations had to be chosen. The Elliptical family was chosen since it has many parameters that can be easily and directly measured to insure that all the internal circuits of ispPAC80 are operating correctly. SPI Power-On Condition The SPI shift register is always reset to all zeroes when an ispPAC80 powers on. That means that if the ENSPI pin is high at power on, the initial configuration will be set to a gain of 1X (0dB) and configuration "A" is selected as the "wake-up" configuration. The only way to prevent this behavior would be to hold the ENSPI pin low while applying power to the device. Because this is usually impractical, it is advised that if the ispPAC80 is used in SPI mode that it be reloaded to the desired first configuration every time power is cycled to the device and/or that R43 100K C231 R11 100K Rin 100K Vin A1 C1 R12 -100K V1 C213 L2 R23 100K C3 R34 -100K C453 C435 L4 R54 -200K R55 200K A2 V2 A3 R45 100K C5 V3 A4 V4 ... A5 Vout VOUT = VIN -2G (L2 L4 C4 C2)s4 + (( L2 G2 C2) + (G 2 L4 C4) ) s 2 + G4 -(L2 C4 2 L4 C1) + 2( L2 C1 C3 L4 C5) - 2(C22 L2 L4 C5)s 5 + -(L2 G C4 2 L4) + (L2 C1 C3 L4 G) - (C22 L2 L4 G) + 2(L2 G C3 L4 C5)s 4 + (L2 C1 C3 G2 ) + (L2 G2 C3 L4) - (G2 L4 C4 2 ) + 2(G2 L4 C5 C3) - 4(G2 L4 C5 C2) -2(L2 C1 C4 G2 ) + 2(G2 C1 L4 C5) + 2(L2 C5 G2 C1)-(C2 2 L2 G2 )s 3 2(L2 C5 G3 ) - 2(G3 L4 C2) + (G3 L4 C3) + (L2 G3 C1) + 2(G3 L4 C5) - 2( L2 C4 G3 ) + (G3 C1 L4) + (L2 C3 G3 ) s 2 + + 2(G4 C5) + (G4 C3) - 2(G4 C4) + (G4 L4) + (G4 C1) + (L2 G4 ) - 2(G4 C2) s + 2 G5 9 Specifications ispPAC80 Theory of Operation (Continued) the "A" configuration memory hold the desired "wake up" filter response. Table 1. SPI Control Bit Sequence bit-7 PG2 bit-6 PG1 bit-5 A/B bit-4 CAL bit-3 X bit-2 X bit-1 X bit-0 X A/B Configuration Two complete configurations can be stored in the E2 memory of the ispPAC80. Selection of either the "A" or "B" configuration in real time is accomplished with the device in the SPI interface mode (ENSPI pin = logic high). An eight-bit string is read into the ispPAC80 in the following order: four "don't care" bits followed by a CAL command bit, the A/B configuration setting and gain bits PG2 and PG1. Table 2. Gain Bit Settings Gain Setting 1X (0dB) 2X (6dB) 5X (14dB) 10X (20dB) PG2 0 0 1 1 PG1 0 1 0 1 JTAG User Bits There are a number of user configured E2 bits that control various aspects of and can all be accessed somewhere in either the pull-down menus or directly in the schematic design entry screen of the PAC-Designer software interface to the ispPAC80. See the online help associated with the ispPAC80 in PAC-Designer for more details of how to set/program various operation modes. The list of control E2 bits available is listed in Table 3. Table 3. JTAG User Configuration Bits Symbol FreqRange Bit Name Hi/Lo Frequency Range Bit Description Depending on the corner frequency, the frequency range bit is automatically set from within PAC-Designer to optimize the transfer function response of the ispPAC80. Exists for both the A and B user strings. Can be overridden from within PAC-Designer from the edit symbol dialog. These are uncommitted E2 bits that can be used to store device information for future reference. The ispPAC80 contains 21 UES bits. These bits are accessible from within PAC-Designer by using the Edit Symbol, UES Bits command. Part of user configuration string A only. Varying length data words for each of the 7 configuration capacitors of the ispPAC80. There is a complete set of 70 bits total for each user configuration string, A and B. With the A/B bit set to "A" (a logic 0), the device will power up in the configuration stored in user string A. The designations of A or B would have been determined initially in the design environment using PAC-Designer. It is also possible to designate the B user string as the initial or "wake up" configuration, although this is not recommended as it blocks the algorithm required to do a "blind" verification of the A configuration of a previously programmed device. This is determined from within PAC-Designer in the edit symbol dialog. Contained only in the A configuration string. Can also be modified under SPI control. Refer to Table 2 for bit setting specifics. Setting this bit causes all subsequent readouts of the device configuration to be disabled (JTAG Verify commands). Can be reset by performing a JTAG user (USRA) bulk erase commands and reprogramming the device. This feature is used to prevent unauthorized readout of the device's configuration. UES Bits User Electronic Signature Cap Bits Capacitor Selection Bits A/B Bit Initial Configuration Select PG1 & PG2 Bits ESF Programmable Gain Bits Electronic Security Fuse 10 Specifications ispPAC80 Theory of Operation (Continued) Differential I/O. Differential peak-peak voltage is determined by knowing the signal extremes on both differential input or output pins. For example, if V(+) equals 4V and V(-) equals 1V, the differential voltage is defined as V(+) - V(-) = Vdiff, or 4V - 1V = +3V. Since either polarity can exist on differential I/O pins, it is also possible for the opposite extreme to exist and would mean when V(+) equals 1V and V(-) equals 4V, the differential voltage is now 1V - 4V = -3V. To calculate the differential peak-peak voltage or full signal swing, the absolute difference between the two extreme Vdiff's is calculated. Using the previous examples would result in |(+3V) - (-3V)| = 6V. It can be immediately seen that true differential signals result in a doubling of usable dynamic range. For more explanation of this and other differential circuit benefits, please refer to application note AN6019. Single-ended Input. To connect the ispPAC80 differential input to a single-ended signal, one of the differential inputs needs to be connected to a DC bias, preferably VREFOUT. The input signal must either be AC coupled or have a DC bias equal to the DC level of the other input. Since the input voltage is defined as VIN+- VIN-, the common mode level is ignored. The signal information is only present on one input, the other being connected to a voltage reference. Single-ended Output. Connecting the output to a singleended circuit is simpler still. Simply connect one-half of the differential output, but not the other. Either output conveys the signal information, just at half the magnitude of the differential output. The DC level of the singleended output will be VREFOUT. If the load is not AC coupled and is at a DC potential other than VREFOUT, the load draws a constant current. Using one of the differential outputs halves the available output voltage swing (3Vp-p versus 6Vp-p). If the load requires DC current, the amount available for voltage swing is reduced. The output is capable of 10mA, so any DC current raises the minimum allowable load impedance. The input common-mode voltage is VCM = (VCM+ + VCM-)/2. When the value of VCM is 2.5V, there are no further input restrictions other than the previously mentioned clipping consideration. This is easily achieved when the input signal is true differential and referenced to 2.5V. When VCM is not 2.5V and the gain setting is greater than one, distortion will occur when the maximum input limit is reached for a particular gain. The lowest VCM for a given gain setting is expressed by the formula, VCM- = 0.675V + 0.584G*VIN where G is the gain setting and VIN is the peak input voltage, expressed as |VIN+ - VIN-| and the highest VCM is VCM+ = 5.0V - VCM- where 5V is the nominal supply voltage. In Table 4, the maximum VIN for a given VCM- to VCM+ range is given. If the maximum VIN is known, find the equivalent or greater value under the appropriate gain column and the widest range for VCM will be found horizontally across in the left-most two columns. Only a VCM range equal to or less than this will give distortionfree performance. Conversely, if the maximum VCM range is known, the largest acceptable peak value of VIN can be found in the corresponding gain column. All values of VIN less than this will give full rated performance. Table 4. Input Common-Mode Voltage Range Limitations Input Voltage Magnitude (Volts-Peak) VCM1.000 1.100 1.200 1.300 1.400 1.500 1.600 1.700 1.800 1.900 2.000 2.100 2.200 2.300 2.400 2.426 2.500 VCM+ 4.000 3.900 3.800 3.700 3.600 3.500 3.400 3.300 3.200 3.100 3.000 2.900 2.800 2.700 2.600 2.574 2.500 G=1 0.557 0.728 0.899 1.071 1.242 1.413 1.584 1.756 1.927 2.098 2.270 2.441 2.612 2.783 2.955 3.000* 3.126 G=2 0.278 0.364 0.450 0.535 0.621 0.707 0.792 0.878 0.964 1.049 1.135 1.220 1.306 1.392 1.477 1.500* 1.563 G=5 0.111 0.146 0.180 0.214 0.248 0.283 0.317 0.351 0.385 0.420 0.454 0.488 0.522 0.557 0.591 0.600* 0.625 G=10 0.056 0.073 0.090 0.107 0.124 0.141 0.158 0.176 0.193 0.210 0.227 0.244 0.261 0.278 0.295 0.300* 0.313 Input Common-Mode Voltage Range For the ispPAC80, both maximum input signal range and corresponding common-mode voltage range are a function of the input gain setting. The maximum input voltage times the gain of an individual PACblock cannot exceed the output range of that block or clipping will occur. The maximum guaranteed input range is 1V to 4V, with an extended typical range of 0.7V to 4.3V for a 5V supply voltage. *Peak input voltage for guaranteed performance at a given gain setting. 11 Specifications ispPAC80 Software-Based Design Environment Design Entry Software Designers configure the ispPAC80 and verify its performance using PAC-Designer, an easy-to-use, Microsoft Windows compatible program. Circuit designs are entered graphically and then verified, all within the PAC-Designer environment. Full device programming is supported using PC parallel port I/O operations and a download cable connected to the serial programming interface of the ispPAC80. A database of filter configurations is included with thousands of possible implementations to choose from. In addition, comprehensive on-line and printed documentation is provided that covers all aspects of PAC-Designer operation. The PAC-Designer schematic window, shown in Figure 2, provides access to all configurable ispPAC80 elements via its graphical user interface. All analog input Figure 2. Initial PAC-Designer Schematic Design Entry Screen and output pins are represented. Static or nonconfigurable pins such as power, ground, VREFOUT, and the serial digital interface are omitted for clarity. Any element in the schematic window can be accessed via mouse operations as well as menu commands. When completed, configurations can be saved, simulated, and downloaded to devices. PAC-Designer operation can be automated and extended by using custom-designed Visual BasicTM programs that set the interconnections and the parameters of ispPAC products. More information on this and other topics is included in the on-line documentation as well as the PAC-Designer Getting Started Manual. Design1 IN IA 1, 2, 5, 10 5th Order Lowpass Filter PACell A/B 2:1 Mux OA OUT Type=Butterworth Fc=500.0kHz Cfg A Fp= PB Ripple= SB Atten.= C1 Cfg A Cfg B 1.970 32.113 C2 0.000 4.890 L2 5.140 38.492 C3 Type=Elliptic Fc=50.0kHz Cfg B Fp=75.0kHz PB Ripple=0.1dB SB Atten.=-40.0dB C4 0.000 14.726 L4 5.256 28.512 C5 1.020 17.486 6.332 66.918 12 Specifications ispPAC80 Software-Based Design Environment (Continued) Design Simulation Capability A powerful feature of PAC-Designer is its simulation capability, enabling quick and accurate verification of circuit operation and performance. Once a circuit is configured via the interactive design process, gain and phase response between any input and output can then be determined. This function is part of the simulator capability which derives a transfer equation between the two points and then sweeps it over the user-specified frequency range. Figure 3 shows a typical screen plot of the gain/phase simulator. In it are the input to output response curves of an Elliptical and a Butterworth reFigure 3. PAC-Designer Simulation Plot Screen PAC Designer - [Design1:2] File Edit View Curve Tools Options Window Help sponse stored in configuration A and B respectively. These are the two options specified in the design screen window shown in Figure 2. The simulator is capable of displaying up to four separate input to output responses. This allows multiple signals to be viewed as well as intermediate results of component changes so performance comparisons can be made. There is also a user-positioned crosshair cursor that intersects the curves on the plot, and reads out the gain and frequency in the lower right hand corner of the plot window when activated. -20 -60 -100 -140 1K 0 -60 -120 -180 -240 -300 -360 1K 10K 100K 1M 10M 10K 100K 1M 10M Ready Curve:1 Vout1/Vin1 13 Specifications ispPAC80 In-System Programmability In-System Programming The ispPAC80 is an in-system programmable device. This is accomplished by integrating all high voltage programming circuitry on-chip. Programming is performed through a 5-wire, IEEE 1149.1 compliant serial port interface at normal logic levels. Once a device is programmed, all configuration information is stored on-chip, in non-volatile E2CMOS memory cells. The specifics of the IEEE 1149.1 serial interface are described in the interface section of this data sheet. the device, so the original configuration can not be examined once programmed. Usage of this feature is optional. Production Programming Support Once a final configuration is determined, an ASCII format JEDEC file is created using the PAC-Designer software. Devices can then be ordered through the usual supply channels with the user's specific configuration already preloaded into the devices. By virtue of its standard interface, compatibility is maintained with existing production programming equipment, giving customers a wide degree of freedom and flexibility in production planning. User Electronic Signature A user electronic signature (UES) feature is included in the E2 memory of the ispPAC80. It contains 21 bits that can be configured by the user to store unique data such as ID codes, revision numbers or inventory control data. Evaluation Fixture Included in the basic ispPAC80 Design Kit is an engineering prototype board that can be connected to the parallel port of a PC. It demonstrates proper layout techniques for the ispPAC80 and can be used in real time to check circuit operation as part of the design process. Input and output connections as well as a "breadboard" circuit area are provided to speed debugging of the circuit. Electronic Security An electronic security "fuse" (ESF) bit is provided in every ispPAC80 device to prevent unauthorized readout of the E2CMOS user bit patterns. Once programmed, this cell prevents further access to the functional user bits in the device. This cell can only be erased by reprogramming Figure 4. Configuring the ispPAC80 "In-System" from a PC Parallel Port PAC-Designer Software Other System Circuitry ispDownload Cable (6') 4 ispPAC80 Device 14 Specifications ispPAC80 IEEE Standard 1149.1 Interface Serial Port Programming Interface Communication with the ispPAC80 is facilitated via an IEEE 1149.1 test access port (TAP). It is used by the ispPAC80 as a serial programming interface, and not for boundary scan test purposes. There are no boundary scan logic cells in the ispPAC80 architecture. This does not prevent the ispPAC80 from functioning correctly, however, when placed in a valid serial chain with other IEEE 1149.1 compliant devices. A brief description of the ispPAC80 serial interface follows. For complete details of the reference specification, refer to the publication, Standard Test Access Port and Boundary-Scan Architecture, IEEE Std 1149.1-1990 (which now includes IEEE Std 1149.1a-1993). out of the user register to verify the current ispPAC20 configuration. Instructions exist to access all data registers and perform internal control operations. For compatibility between compliant devices, two data registers are mandated by the IEEE 1149.1 specification. Others are functionally specified, but inclusion is strictly optional. Finally, there are provisions for optional data registers defined by the manufacturer. The two required registers are the bypass and boundary-scan registers. For ispPAC80, the bypass register is a 1-bit shift register that provides a short path through the device when boundary testing or other operations are not being performed. The ispPAC80, as mentioned, has no boundary scan logic and therefore no boundary scan register. All instructions relating to boundary scan operations place the ispPAC80 in the BYPASS mode to maintain compliance with the specification. The optional identification register described in IEEE 1149.1 is also included in the ispPAC80. One additional data register included in the TAP of the ispPAC80 is the Lattice defined user register. Figure 5 shows how the instruction and various data registers are placed in an ispPAC80. Overview An IEEE 1149.1 test access port (TAP) provides the control interface for serially accessing the digital I/O of the ispPAC80. The TAP controller is a state machine driven with mode and clock inputs. Under the correct protocol, instructions are shifted into an instruction register which then determines subsequent data input, data output, and related operations. Device programming is performed by addressing the user register, shifting data in, and then executing a program user instruction, after which the data is transferred to internal E2CMOS cells. It is these non-volatile cells that determine the configuration of the ispPAC80. By cycling the TAP controller through the necessary states, data can also be shifted Figure 5. ispPAC80 TAP Registers USER REGISTER ID REGISTER BYPASS REGISTER INSTRUCTION REGISTER TAP Controller Specifics The TAP is controlled by the Test Clock (TCK) and Test Mode Select (TMS) inputs. These inputs determine whether an Instruction Register or Data Register operation is performed. Driven by the TCK input, the TAP consists of a small 16-state controller design. In a given state, the controller responds according to the level on the TMS input as shown in Figure 16. Test Data In (TDI) and TMS are latched on the rising edge of TCK, with Test Data Out (TDO) becoming valid on the falling edge of TCK. There are six steady states within the controller: Test-Logic-Reset, Run-Test/Idle, Shift-Data-Register, Pause-Data-Register, Shift-Instruction-Register, and Pause-Instruction-Register. But there is only one steady state for the condition when TMS is set high: the TestLogic-Reset state. This allows a reset of the test logic within five TCKs or less by keeping the TMS input high. Test-Logic-Reset is the power-on default state. When the correct logic sequence is applied to the TMS and TCK inputs, the TAP will exit the Test-Logic-Reset state and move to the desired state. The next state after Test-Logic-Reset is Run-Test/Idle. Until a data or instruction scan is performed, no action will occur in Run-Test/ Idle (steady state = idle). After Run-Test/Idle, either a data or instruction scan is performed. The states of the Data and Instruction Register blocks are identical to each other differing only in their entry points. When either block TEST ACCESS PORT (TAP) LOGIC OUTPUT LATCH TDI TCK TMS TDO MUX 15 Specifications ispPAC80 IEEE Standard 1149.1 Interface (Continued) is entered, the first action is a capture operation. For the Data Registers, the Capture-DR state is very simple: it captures (parallel loads) data onto the selected serial data path (previously chosen with the appropriate instruction). For the Instruction Register, the Capture-IR state will always load the IDCODE instruction. It will always enable the ID Register for readout if no other instruction is loaded prior to a Shift-DR operation. This, in conjunction with mandated bit codes, allows a "blind" interrogation of any device in a compliant IEEE 1149.1 serial chain. From the Capture state, the TAP transitions to either the Shift or Exit1 state. Normally the Shift state follows the Capture state so that test data or status information can be shifted out or new data shifted in. Following the Shift state, the TAP either returns to the Run-Test/Idle state via the Exit1 and Update states or enters the Pause state via Exit1. The Pause state is used to temporarily suspend the shifting of data through either the Data or Instruction Register while an external operation is performed. From the Pause state, shifting can resume by reentering the Shift state via the Exit2 state or be terminated by entering the Run-Test/Idle state via the Exit2 and Update states. If the proper instruction is shifted in during a Shift-IR operation, the next entry into Run-Test/Idle initiates the test mode (steady state = test). This is when the device is actually programmed, erased or verified. All other instructions are executed in the Update state. Test Instructions Like data registers, the IEEE 1149.1 standard also mandates the inclusion of certain instructions. It outlines the function of three required and six optional instructions. Any additional instructions are left exclusively for the manufacturer to determine. The instruction word length is not mandated other than to be a minimum of 2-bits, with only the BYPASS and EXTEST instruction code patterns being specifically called out (all ones and all zeroes respectively). The ispPAC80 contains the required minimum instruction set as well as one from the optional instruction set. In addition, there are several proprietary instructions that allow the device to be configured and verified. For ispPAC80, the instruction word length is 5bits. All ispPAC80 instructions available to users are shown in Table 5. BYPASS is one of the three required instructions. It selects the Bypass Register to be connected between TDI and TDO and allows serial data to be transferred through the device without affecting the operation of the Figure 6. Test Access Port (TAP) Contoller State Diagram 1 0 Test-Logic-Rst 0 Run-Test/Idle 1 1 Select-DR-Scan 0 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 0 1 Exit2-DR 1 Update-DR 1 0 1 0 0 0 1 1 1 Select-IR-Scan 0 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 1 Exit2-IR 1 Update-IR 0 0 0 1 1 Note: The value shown adjacent to each state transition in this figure represents the signal present at TMS at the time of a rising edge at TCK. 16 Specifications ispPAC80 IEEE Standard 1149.1 Interface (Continued) Table 5. ispPAC80 TAP Instructions Instruction EXTEST ADDUSR ABE BBE VERA VERB PRGA PRGB ENCAL IDCODE SAMPLE BYPASS Code 00000 00001 00010 00011 00100 00101 00110 00111 01100 01101 11110 11111 Description External test. Default to BYPASS. Address user data register (A or B). User A bulk erase. User B bulk erase. Verify User A data register. Verify User B data register. Program User A data register. Program User B data register. Enable calibration sequence. Read identification data register. Sample/preload. Default to BYPASS. Bypass (connect TDI to TDO). TAP Inst/PAC80 Figure 7. Identification Code (IDCODE) 32-Bit Binary Word for Lattice ispPAC20 MSB LSB XXXX / 0000 0001 0010 0000 / 0000 0100 001 / 1 Part Number JEDEC Manfacturer (16-bits) Identity Code for 0120h = PAC80 Lattice Semiconductor (11-bits) Constant 1 Version (1-bit) (4-bits) 2 Configured per 1149.1-1990 E ispPAC80. The bit code of this instruction is defined to be all ones by the IEEE 1149.1 standard. The required SAMPLE/PRELOAD instruction dictates the Boundary-Scan Register be connected between TDI and TDO. The ispPAC80 has no boundary-scan register, so for compatibility it defaults to the BYPASS mode whenever this instruction is received. The bit code for this instruction is defined by Lattice as shown in Table 5. The EXTEST (external test) instruction is required and would normally place the device into an external boundary test mode while also enabling the Boundary-Scan Register to be connected between TDI and TDO. Again, since the ispPAC80 has no boundary-scan logic, the device is put in the BYPASS mode to ensure specification compatibility. The bit code of this instruction is defined by the 1149.1 standard to be all zeros. The optional IDCODE (identification code) instruction is incorporated in the ispPAC80 and leaves it in its functional mode when executed. It selects the Device Identification Register to be connected between TDI and TDO. The Identification Register is a 32-bit shift register containing information regarding the IC manufacturer, device type and version code (see Figure 7). Access to the Identification Register is immediately available, via a TAP data scan operation, after power-up of the device, or by issuing a Test-Logic-Reset instruction. The bit code for this instruction is defined by Lattice as shown in Table 5. ADDUSR (address user register) instruction is a Lattice defined instruction that selects the user register to be shifted during a Shift-DR operation. Normal operation of a device is not interrupted by this instruction. It precedes a PRGA or PRGB (program user A or B) instruction to shift in a new configuration from the user register into either the A or B configuration memory, and follows a VERA or VERB (verify user A or B) instruction to shift out the current configuration of either A or B configuration memory into the user register. The bit code for this instruction is shown in Table 5. The PRGA and PRGB (program user A or B) are Lattice instructions that enable the data shifted into the user register to be programmed into the non-volatile E2CMOS memory of the ispPAC80 and thereby alter either or both of its two user configurations. The user register is a 96bit shift register that contains all the user-controlled parametric data pertaining to the configuration of the ispPAC80. NOTE: Although the user register length is 96 bits, only the "A" configuration is that long. The device gain setting bits, UES bits, and security fuse bit are all part of the "A" configuration memory and are not stored at all in "B" memory, which only contains the unique capacitor settings of that configuration. When initially programming or reprogramming the ispPAC80 with software other than PAC-Designer, or an authorized third-party programmer (e.g., via microcontroller, refer to the Lattice application note covering the required algorithms necessary for complete JTAG device programming control of the ispPAC80, specific bit assignments, word lengths, etc.). Normal operation of the device is interrupted during the actual programming time. A programming operation does not begin until entry of the Run-Test/Idle state. The time required to insure data 17 Specifications ispPAC80 IEEE Standard 1149.1 Interface (Continued) retention is given in the TAP signal specifications table. The user must ensure that the recommended programming times are observed. The bit code for these instructions is shown in Table 5. The last Lattice instructions are ABE and BBE (user A or B bulk erase). Operation of the device is interrupted during an ABE or BBE, during which all inputs are disconnected and all outputs driven to VREFOUT (2.5V). To economize internal circuitry, programming can only be selectively done in one direction (from zeroes to ones). The ABE and BBE are used to return all user bits to a zero state at the same time. An ABE or BBE usually proceeds a PRGA or PRGB operation, otherwise one to zero changes would not be implemented. It can also be used to erase all configuration information from a device and is the default condition of parts shipped from the factory. The same programming time constraints apply to ABE and BBE as for PRGA and PRGB. The bit code for this instruction is shown in Table 5. The ADDUSR, BYPASS, EXTEST, IDCODE and SAMPLE/PRELOAD instructions are all executed in the Update-IR state. Other instructions: PRGUSR, VERUSR and UBE are executed upon entry of the Run-Test/Idle state. It is recommended that when all serial interface operations are completed, the TAP controller be reset and left in the Test-Logic-Reset state (the power-up default) and the TCK and TMS inputs idled. This will insure the best analog performance possible by minimizing the effects of digital logic "feed-through." VERA and VERB (verify user A or B) are the next Lattice instructions and cause the current A or B configurations of the ispPAC80 to be loaded into the user register. This operation doesn't interrupt operation of the device. The current configuration of either the A or B configuration memory can then be shifted out of the user register immediately after an ADDUSR instruction is executed. NOTE: The verification of memory configuration "A" is possible only when the A/B bit is set to a logic 0. This must be taken into account if verify will be performed at a later time on parts with unknown configurations (refer to the Lattice application note covering the required algorithms necessary for complete JTAG device programming control of the ispPAC80, specific bit assignments, word lengths, etc.). If the A/B bit has been set to a logic 1, it will not be possible to do a VERA command properly. The bit code for this instruction is shown in Table 5. ENCAL (enable calibration) is a Lattice instruction that enables the start of an auto-calibration sequence. This operation causes all outputs of the device to go to 2.5V until the calibration sequence is completed (see timing specifications). As with the programming instructions above, calibration does not begin until entry of the RunTest/Idle state. The completion of the calibration is not dependent, however, on any further TAP control. This means the state of the TAP can be returned immediately to the Test-Logic-Reset state. The only consideration would be to not clock the TAP during critical analog operations. The first several milliseconds of the calibration routine are consumed waiting for configurations to settle, though, leaving more than enough time to clock the TAP back to the Test-Logic-Reset state. The bit code for this instruction is shown in Table 5. 18 Specifications ispPAC80 Package Diagrams 16-Pin Plastic PDIP Dimensions in Inches MIN./MAX. (Dimensions in millimeters, shown in parenthesis, are for reference only) .240 / .260 (6.10 / 6.60) .300 / .325 (7.61 / 8.25) .745 / .755 (18.92 / 19.18) .008 / .012 (.20 / .31) .195 (4.95) MAX .015 (.38) MIN .125 / .135 (3.17 / 3.43) 0-15 .055 /.065 (1.40 / 1.65) .015 /.022 (.38 / .56) .100 (2.54) BSC 16-Pin Plastic SOIC Dimensions in Inches MIN./MAX. (Dimensions in millimeters, shown in parenthesis, are for reference only) .292 (7.42) .299 (7.59) .400 (10.16) .410 (10.41) .050 (1.27) BSC .014 (.35) .019 (.48) .097 (2.46) .104 (2.64) .402 (10.21) .412 (10.46) .0050 (.127) .0115 (.292) 0 8 .024 (.61) .040 (1.02) .0091 (.23) .0125 (.32) 19 |
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